The present invention relates to the field of semiconductor processing and more particularly to a method of forming an interlayer dielectric in an integrated circuit.
One prior method of forming an interlayer dielectric (ILD) in an integrated circuit, described in the pending U.S. patent application entitled xe2x80x9cCapped Interlayer Dielectric for Chemical Mechanical Polishingxe2x80x9d, with Ser. No. 08/536,007 and assigned to the present assignee, is illustrated in FIGS. 1a through 1h. FIG. 1a is an illustration of a cross sectional view of semiconductor devices 100 formed on silicon substrate 101 and isolated from each other by field oxide region 102.
FIG. 1b shows the substrate of FIG. 1a covered by phosphosilicate glass (PSG) 103, or alternatively, a borophosphosilicate glass layer. PSG layer 103 is formed with a conventional deposition technique that exhibits superior gap filling ability, such as atmospheric or subatmospheric chemical vapor deposition.
As shown in FIG. 1b, the top surface 104 of PSG layer 103 is nonplanar due to the underlying topography created by devices 100 and filed field oxide regions 102. Therefore, the top surface 104 of PSG layer 103 is planarized by chemical mechanical polishing (CMP) to create planar top surface 105 of PSG layer 103 as shown in FIG. 1c. Since CMP removes denser layers slower than less dense layers, PSG layer 103 is densified prior to the CMP step to reduce the removal rate, thereby increasing process controllability. Also, the thickness of PSG layer 103 as deposited is much greater than the post CMP thickness to provide a large margin for variation in the CMP process. Typical thicknesses of PSG layer 103 are 18,000 A as deposited and 4,500 A post CMP.
FIG. 1d shows the substrate of FIG. 1c after cap layer 106 is deposited over planarized PSG layer 103. Cap layer 106 is an undoped oxide layer formed by plasma enhanced chemical vapor deposition with tetraethyl orthosilicate as the silicon source. Cap layer 106 is denser than PSG layer 103, which allows cap layer 106 to serve as moisture barrier and a polish stop for a subsequent tungsten CMP step involved in forming tungsten plugs. Also, cap layer 106 is thinner than PSG layer 103, approximately 2,000 A compared to 4,500 A.
FIG. 1e shows the substrate of FIG. 1d after openings 107 have been formed through cap layer 106 and PSG layer 103 to prepare for making electrical contact to underlying devices 100. FIG. 1f shows the substrate of FIG. 1e after plug layer 108 has been deposited, filling openings 107. Plug layer 108 is tungsten over a composite adhesion layer of titanium nitride over titanium. FIG. 1g shows the substrate of FIG. 1f after plug layer 108 has been polished to form plugs 109. Finally, FIG. 1h shows the substrate of FIG. 1g after metal interconnects 110 are formed on cap layer 106.
Although this prior method of forming a PSG ILD is compatible with a CMP plug process, the ILD process is more complex than that of a single layer ILD. Therefore, what is desired is a less complex method for forming a PSG ILD layer that is compatible with a CMP plug process.
A method of forming an interlayer dielectric on a semiconductor device is disclosed. First, an insulating layer comprising phosphorous is deposited on the semiconductor device. Then, another insulating layer which is denser than the first insulating layer is deposited. Finally, the planarity of the second insulating layer is increased using chemical mechanical polishing.